EP7311 Datasheet, PDF (13/54 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

EP7311
High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
SDCLK rising edge to SDCS assert delay time
SDCLK rising edge to SDCS deassert delay time
SDCLK rising edge to SDRAS assert delay time
SDCLK rising edge to SDRAS deassert delay time
SDCLK rising edge to SDRAS invalid delay time
SDCLK rising edge to SDCAS assert delay time
SDCLK rising edge to SDCAS deassert delay time
SDCLK rising edge to ADDR transition time
SDCLK rising edge to ADDR invalid delay time
SDCLK rising edge to SDMWE assert delay time
SDCLK rising edge to SDMWE deassert delay time
DATA transition to SDCLK rising edge time
SDCLK rising edge to DATA transition hold time
SDCLK rising edge to DATA transition delay time
Symbol
t_CSa
t_CSd
t_RAa
t_RAd
t_RAnv
t_CAa
t_CAd
t_ADv
t_ADx
t_MWa
t_MWd
t_DAs
t_DAh
t_DAd
Min
0
−3
1
−3
2
−2
−5
−3
−2
−2
−4
-
-
0
Typ
2
2
3
1
4
2
0
1
2
1
0
-
-
-
Max
4
10
7
10
7
5
3
5
5
5
4
2
1
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS506PP1
©Copyright Cirrus Logic, Inc. 2003
(All Rights Reserved)
13