EP7311 Datasheet, PDF(17/54 Page) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

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EP7311 Datasheet, PDF (17/54 Pages) Cirrus Logic – HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH SDRAM AND ENHANCED DIGITAL AUDIO INTERFACE

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SDRAM Refresh Cycle

EP7311

High-Performance, Low-Power System on Chip

SDCLK

SDCS

SDRAS

SDCAS

SDATA

ADDR

SDQM

[3:0]

SDMWE

tCSa

tRAa

tCSd

tRAd

tCAa

tCAd

Figure 6. SDRAM Refresh Cycle Timing Measurement

Note:

1. Timings are shown with CAS latency = 2

2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal

DS506PP1

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