CS35L32 Datasheet, PDF (37/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
7.6 Power Control 2
7.6 Power Control 2
Address 0x07
R/W
7
6
5
4
3
2
1
0
PDN_VMON PDN_IMON PDN_VPMON
—
SDOUT_3ST
—
Default
1
1
1
0
1
0
0
0
Bits Name
Description
7 PDN_ Power-down VMON ADC. Configures the power state of the ADC front end and the ADC used to monitor the VSENSE± input
VMON pins to create the VMON data.
0 Powered up
1 (Default) Powered down
6 PDN_ Power-down IMON ADC. Configures the power state of the ADC front end, and the ADC, and range selection circuitry used to
IMON monitor the ISENSE± input pins to create the IMON data.
0 Powered up
1 (Default) Powered down
5 PDN_ Power-down VPMON ADC. Configures the ADC front end power state and the ADC used to monitor the VP supply pin to create
VPMON the VP data.
0 Powered up
1 (Default) Powered down
4
— Reserved
3 SDOUT_ Tristate the ADSP SDOUT path. Configures the Hi-Z state of the ADSP SDOUT output path.
3ST 0 SDOUT is powered up.
1 (Default) SDOUT is Hi-Z.
2:0 — Reserved
7.7 Clocking Control
Address 0x08
R/W
7
6
5
MCLKDIS
MCLKDIV2
4
3
2
—
1
0
RATIO
Default
0
1
0
0
0
0
0
0
Because clock rates must be stable when the device is powered up, the device must be powered down before changing clock rates.
Bits Name
Description
7 MCLKDIS MCLK disable. Configures the state of MCLK_INT before its fan-out to all the internal circuitry.
0 (Default) On
1 Off. Disables the clock tree to save power when the device is powered down. Set only after the device powers down.
6 MCLKDIV2 MCLK divide by 2. Configures a divide between the input pin MCLK and the derived core clock, MCLK_INT.
0 No divide
1 (Default) Divide by 2
5:1
—
Reserved
0 RATIO f_MCLK(INT)/f_LRCK ratio. Table 3-12 shows the effect of these settings on the Master Mode duty cycle.
0 (Default)128
1 125
Application: Refer to Section 4.11.2, “Master and Slave Timing.”
7.8 Low Battery Thresholds
Address 0x09
R/W
Default
7
6
—
0
0
5
4
LOWBAT_TH[1:0]
1
0
3
2
1
0
LOWBAT_RECOV[2:0]
—
0
1
1
0
Bits Name
Description
7:6
—
Reserved
5:4 LOWBAT_ Low battery nominal threshold, falling VP. See Table 3-3 for accuracy specifications.
TH
00 3.1 V
01 3.2 V
10 (Default) 3.3 V
11 3.4 V
3:1 LOWBAT_ Low battery nominal recovery threshold, rising VP. See Table 3-3 for accuracy specifications.
RECOV _{000 Reserved}
010 3.3 V
100 3.5 V
110–111 3.6 V
001 3.2 V
011 (Default) 3.4 V
101 3.6 V
0
—
Reserved.
DS963F5
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