CS35L32 Datasheet, PDF (12/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
3 Characteristics and Specifications
Table 3-9. PSRR Characteristics
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = VP, amp gain = 12 dB, GNDA = GNDP = 0 V, T_A = +25°C.
Parameters
Conditions
Noise
Noise
Noise
Noise
Injected Into Measured On Amplitude (mV) Frequency (Hz)
Min
Typical
Max
Speaker amplifier
VBST = VP
VA
SPKOUT±
100
217
—
75
—
PSRR
1k
—
75
—
20k
—
70
—
VP
SPKOUT±
100
217
—
70
—
1k
—
70
—
20k
—
55
—
VPMON PSRR
VBST = VP
VA
SDOUT
100
217
—
36
—
1k
—
36
—
20k
—
33
—
VSENSE± PSRR ¹
VBST = VP
VA
SDOUT
100
217
—
60
—
1k
—
60
—
20k
—
50
—
ISENSE± PSRR
VBST = VP
VA
SDOUT
100
217
—
60
—
1k
—
60
—
20k
—
60
—
Units
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
1.The speaker voltage monitor has a lower PSRR because its input path has an attenuation of 16.6 dB. The PSRR specification is referred to the input
signal and, as such, includes the loss of 16.6 dB.
Table 3-10. Power Consumption
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = VP, GNDA = GNDP = 0 V, T_A = +25°C.
Use Configuration
Powered up _{RESET asserted, MCLK, SCLK, LRCK inactive}
(PDN_BST = 00) _{IN+ IN– shorted to ground, LEDs off, monitors powered down1}
No C_OUT
IN+ IN– shorted to ground, LEDs off, monitors powered down ¹ C_OUT = 470 pF (See Fig. 2-1)
IN+ IN– shorted to ground, LEDs off, monitors powered up ¹
No C_OUT
IN+ IN– shorted to ground, LEDs off, monitors powered up ¹ C_OUT = 470 pF See Fig. 2-1)
Boost Mode _{RESET asserted, MCLK, SCLK, LRCK inactive}
bypass
(PDN_BST = 01)
.
IN+ IN– shorted to ground, LEDs off, monitors powered down ¹
IN+ IN– shorted to ground, LEDs off, monitors powered down ¹
No C_OUT
C_OUT = 470 pF (See Fig. 2-1)
IN+ IN– shorted to ground, LEDs off, monitors powered up ¹
No C_OUT
IN+ IN– shorted to ground, LEDs off, monitors powered up ¹ C_OUT = 470 pF See Fig. 2-1)
Typical Current
i_VP
i_VA
Units
1
1
A
3270 390
A
4275 390
A
3360 1435
A
4360 1435
A
1
1
A
1983 390
A
3093 390
A
2074 1435
A
3185 1435
A
1.Refer to Section 7.6 for configuring monitor power down
Table 3-11. Switching Specifications: Power, Reset, Master Clocks
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, T_A = +25°C, GNDA = GNDP = 0 V. Fig. 2-1 shows typical
connections; GNDA = GNDP = 0 V. Section 9 describes some parameters in detail; input timings are measured at V_IL and V_IH thresholds; output timings
are measured at V_OL and V_OH thresholds (see Table 3-8).
Parameters
Symbol ¹ Min Max Units
Power supplies ²
Reset ²
Power supply ramp up/down
RESET low (logic 0) pulse width
t_PWR-RUD
—
100 ms
t_RLPW
1
—
ms
RESET hold time after power supplies ramp up
t_RH(PWR-RH)
1
—
ms
RESET setup time before power supplies ramp down
t_RS(RL-PWR)
1
—
ms
RESET rising edge to control-port active
t_IRS
[3]
—
ns
Master clocks
MCLK frequency ⁴
MCLK duty cycle
f_MCLK
D_MCLK
—
12.3 MHz
45
55
%
1.Power and reset sequencing
VOPERATING
VMIN
tPWR-RUD
tPWR-RUD
t_PWR-
RUD
tPWR-RUD
GND
RESET
1^st
Supply
Up
Last
Supply
Up
1^st
Supply
Down
Last
Supply
Down
tRH(PWR-RH) tIRS
Internal supplies stable
tRS(RL-PWR)
Control port active
2.VP supply may be applied or removed independently of RESET and the other power rails. See Section 4.1 for additional details.
3.The RESET rising-edge-to-control-port-active timing, t_irs, is specified in Table 3-13.
4.Maximum frequency for highest supported nominal rate is indicated. The supported nominal serial port sample rates are found in Section 4.11.2.
12
DS963F5