CS35L32 Datasheet, PDF (15/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

4 Functional Description
CS35L32
4 Functional Description
See Section 4.6 “Boost Converter.”
SPKR
See Section 4.9 “LED Driver.”
VA
VP VBST SW
IREF+ _SUPPLY
FLEN FLINH FLOUT1 FLOUT2/AD0
FILT+
IN+
IN–

ADC
Current
Sense
Bandgap
Voltage
Generation
VCOM
Current Mode Synchronous
Boost Controller _{Soft Ramp}
Low Battery ManagementSee Section 4.4.
VREF
Generation
VREF
+
–
9,12,15, or
18 dB + Mute
Class G
I²C Class G Override
Class D Front End
∆Σ Class D Modulator
Short Circuit Protection
See Section 4.3.
Class D Power Stage
SPKR SUPPLY
MCLK
GNDA
See
Section 4.11
“Audio/Data
Serial Port
(ADSP).”
Error
Watchdog
Serial Port
Clock Generation
See Section 4.8,
“Signal Monitoring.”
Range
Scaling

ADC

ADC
LRCK _SerS_iaC_lL_AK _{udio/Data PortSee Section 4.11.}
Level Shifters
Control,
Sensing,
and Fault
Protection
Flash LED Current Driver
GNDPLED
Temperature Overtemp
Sensor
Protection
Power
Budgeting
See
Section 4.10,
“Power
Budgeting.”
VMON ADC _VSENSE+
Front End
LP _VSENSE–
IMON ADC
Front End
ISENSE+
LP _ISENSE–
I²C Control Port
See Section 4.14.
See
Section 4.7.
SPKOUT+
SPKOUT–/
VSENSE–
GNDP
ISENSE+
ISENSE–/
VSENSE+
See Section 4.13,
“Device Clocking.” SCLK
LRCK
SDOUT
SCL
SDA
Figure 4-1. CS35L32 Block Diagram
RESET
INT ^{See Section 4.2.}
4.1 Power Supplies
The VA and VP supplies are required for proper operation of the CS35L32. Before either supply is powered down, RESET
must be asserted. RESET must be held in the asserted state until all supplies are up and within the recommended range.
Timing requirement for RESET during supply power up and power down is described in Table 3-11. The VBST supply is
generated internally (as described in Section 7.12) and connected to the high-power output stage of the Class D amplifier
through two balls: VBST and SPKRSUPPLY. By so doing, the speaker amplifier benefits from the proximity of the external
decoupling capacitor that is connected to the boosted supply.
4.2 Interrupts
Events that require special attention, such as when a threshold is exceeded or an error occurs, are reported through the
assertion of the interrupt output pin, INT. These events are captured within the interrupt status registers. Events can be
individually masked by setting corresponding bits in the interrupt mask registers. Table 4-1 lists interrupt status and mask
registers. The configuration of mask bits determines which events cause the immediate assertion of INT:
• When an unmasked interrupt status event is detected, the status bit is set and INT is asserted.
• When a masked interrupt status event is detected, the interrupt status bit is set, but INT is not affected.
Once INT is asserted, it remains asserted until all unmasked status bits that are set have been read. Interrupt status bits
are sticky and read-to-clear: Once set, they remain set until the register is read and the associated interrupt condition is
not present. If a condition is still present and the status bit is read, although INT is deasserted, the status bit remains set.
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