CS35L32 Datasheet, PDF (14/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
3 Characteristics and Specifications
Table 3-13. Switching Specifications: I²C Control Port
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, T_A = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 =
VA; SDA load capacitance equal to maximum value of C_B specified below; minimum SDA pull-up resistance, R_P(min).¹ Section 9 describes some
parameters in detail. All specifications are valid for the signals at the pins of the CS35L32 with the specified load capacitance; input timings are measured
at V_IL and V_IH thresholds; output timings are measured at V_OL and V_OH thresholds (see Table 3-8).
Parameter
Symbol ²
Min
Max
Units
RESET rising edge to start
SCL clock frequency
Start condition hold time (before first clock pulse)
Clock low time
Clock high time
Setup time for repeated start condition
SDA input hold time from SCL falling ³
SDA output hold time from SCL falling
SDA setup time to SCL rising
Rise time of SCL and SDA
Fall time of SCL and SDA
Setup time for stop condition
Bus free time between transmissions
SDA bus capacitance
t_IRS
f_SCL
t_HDST
t_LOW
t_HIGH
t_SUST
t_HDDI
t_HDDO
t_SUD
t_RC
t_FC
t_SUSP
t_BUF
C_B
500
—
ns
—
400
kHz
0.6
—
µs
1.3
—
µs
0.6
—
µs
0.6
—
µs
0
0.9
µs
0.2
0.9
µs
100
—
ns
—
300
ns
—
300
ns
0.6
—
µs
1.3
—
µs
—
400
pF
1.The minimum R_P and R_{P_I} values (resistors shown in Fig. 2-1) are determined using the maximum level of VA, the minimum sink current strength of
their respective output, and the maximum low-level output voltage V_OL(specified in Table 3-8). The maximum R_P and R_{P_I} values may be determined
by how fast their associated signals must transition (e.g., the lower the value of R_P, the faster the I²C bus is able to operate for a given bus load
capacitance). See the I²C switching specifications in Table 3-13 and the I²C bus specification referenced in Section 13.
2.I²C control-port timing.
RESET
t_IRS
Stop
Start
Repeated
Start
Stop
SDA
t_BUF
SCL
3.Data must be held long enough to bridge the transition time, t_F, of SCL.
t_HDST
t_HIGH
tLOW
t_HDDI,
t_HDDO
tSUD
t_HDST
t_FC
tSUST
tRC
t_SUSP
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