CS35L32 Datasheet, PDF (13/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
3 Characteristics and Specifications
Table 3-12. Switching Specifications: ADSP in I²S Mode
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, T_A = +25°C, Inputs: Logic 0 = GNDA = GNDP = 0 V, Logic 1 =
VA; C_LOAD = 30 pF. Section 9 describes some parameters in detail; input timings are measured at V_IL and V_IH thresholds; output timings are measured
at V_OL and V_OH thresholds (see Table 3-8).
Parameters
Symbol ¹
Min
Max
Units
Slave Mode Input sample rate (LRCK) ²
Fs
—
49
kHz
LRCK duty cycle
—
45
55
%
SCLK frequency
SCLK duty cycle
1/t_Ps
—
64•Fs
Hz
—
45
55
%
Master Mode
LRCK setup time before SCLK rising edge
LRCK hold time after SCLK rising edge
SDOUT time from SCLK to data valid start ³
SDOUT time from SCLK to data valid end ³
OUTPUT sample rate (LRCK) ⁴
t_{SS(LK–SK)}
40
t_{HS(SK–LK)}
20
t_{DataValidStrt}
—
t_DataValidEnd
155
Fs
—
—
ns
—
ns
300
ns
—
ns
[4]
kHz
LRCK duty cycle
—
45
55
%
SCLK frequency
SCLK duty cycle
1/t_PM
—
64•Fs
Hz
RATIO = 0
—
45
55
%
RATIO = 1 ^[5]
—
33
67
%
LRCK setup time before SCLK rising edge
LRCK hold time after SCLK rising edge
SDOUT time from SCLK to data valid start ³
SDOUT time from SCLK to data valid end ³
t_{SM(LK–SK)}
t_{HM(SK–LK)}
t_{DataValidStrt}
t_DataValidEnd
35
20
—
155
—
ns
—
ns
300
ns
—
ns
1.ADSP timing in I²S Mode
LRCK
SCLK
t_{H(SK-LK)}
t_{S(LK-S//K)}
T_P
t_{DataValidStrt}
t_DataValidEnd
SDOUT
Note:
 = “S” or “M”
DataValidWind
2.Clock rates should be stable when the CS35L32 is powered up.
3.Minimum data valid window, as shown in signal diagram, is (SCLKperiod – 300 + 155) ns. For SCLK = 64*Fs =64*48 = 3072 kHz, this is 180 ns.
4.In Master Mode, the output sample rate follows MCLK rate divided down per Table 4-14 and Section 7.7. Any deviation in internal MCLK from the
nominal supported rates is directly imparted to the output sample rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK becomes
a +100-ppm offset in LRCK).
5.If RATIO = 1, the MCLK(INT)-to-LRCK ratio is 125. The device periodically extends SCLK high time to compensate for a fractional MCLK/SCLK ratio
DS963F5
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