CS35L32 Datasheet, PDF (24/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
4.11 Audio/Data Serial Port (ADSP)
4.10.3 Audio and LED Operation
When audio and LEDs are operating simultaneously, the user can select one of the following courses of action:
• By clearing AUDIOGAIN_MNG, if the CS35L32 enters load management mode due to the conditions listed in
Section 4.10, audio gain is reduced once by 3 dB (no reduction for 9-dB gain). If the condition persists, the CS35L32
examines ILED_MNG and responds according to Section 4.10.2. Audio automatically recovers to the original
volume after an LED event.
• By setting AUDIOGAIN_MNG, the user maintains full control over audio gain.
As a default, the boost converter’s output voltage is fixed in Bypass Mode (VBST = VP). The user can set VBOOST_MNG
to any of the nondefault modes for a different boost behavior. In particular, if VBOOST_MNG = 01 in the presence of LED
and audio load power, the CS35L32 adapts for low-power dissipation by automatically reducing the LED driver voltage at
pins FLOUT1 and FLOUT2 and by reducing the boost converter’s output voltage. If VBOOST_MNG = 00 in the presence
of LED and audio-load power, the boost converter’s output voltage is determined by the higher of the two supply
requirements for LED or audio Class G. In such a case, the CS35L32 cannot adapt for low power dissipation if audio
Class G requires a 5-V supply, because of the higher audio signal. Refer to Section 4.3.2.
4.11 Audio/Data Serial Port (ADSP)
The ADSP transmits audio and data to and from the systems processor in traditional I²S Mode. Controls are provided to
advise the device of the rate of the clocks being applied to its inputs when in Slave Mode. Likewise, the same controls are
used to indicate the clock rates to be generated when operating as a clock master.
The serial port I/O interface consists of three signals, described in detail in Table 1-1:
• SCLK: Serial data shift clock
• LRCK: Provides the left/right clock, which identifies the start of each serialized data word and toggles at sample rate
• SDOUT: Serial data output
Onchip Channel
Select
Onchip Serial Port
From Signal
Rate Control Monitoring Blocks
R
L
LRCK
SCLK
Audio Data Serial Port
Level Shifters
LRCK
SCLK
SDOUT
Figure 4-9. Audio/Data Serial Port (ADSP)
Table 4-5 provides links to register fields used to configure components shown in Fig. 4-9.
.
Table 4-5. ADSP Configuration
Register Field
Cross-Reference to Description
PDN_AMP
Section 7.5
SDOUT_3ST
Section 7.6
MCLKDIS, MCLKDIV2, RATIO Section 7.7
M/S
Section 7.13
M_ADSPCLK_ERR
Section 7.16
ADSPCLK_ERR
Section 7.19
4.11.1 Power Up, Power Down, and Tristate
The serial port has separate power-down and tristate controls for its output data path (SDOUT_3ST, see p. 37). ADSP
master/slave operation is governed only by the M/S setting (see p. 39), irrespective of the SDOUT_3ST setting. Table 4-6
describes ADSP operational mode and pin-output driver-state configuration.
24
DS963F5