CS35L32 Datasheet, PDF (11/51 Pages) Cirrus Logic – Boosted Class D Amplifier with Speaker-Protection Monitoring and Flash LED Drivers

CS35L32
3 Characteristics and Specifications
Table 3-7. Signal Monitoring Characteristics
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, 0.1- sense resistor, GNDA = GNDP = 0 V,
T_A = +25°C. Measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, Input Signal = 1 kHz, MCLK_INT = 6 MHz, MCLK_INT is explained in Section 4.13.1
and Section 7.7.
Parameters
Min Typical Max Units
General ADC characteristics
VSENSE± monitoring
characteristics (VMON)
Power-up time: t_PUP(ADC) —
8.5
[1]
ms
Data width —
16
— Bits
Dynamic range (unweighted), VSENSE± = ±5.0 V (10 V_PP) —
60
— dB ²
Total harmonic distortion + noise, –3.8 dBFS ³ —
–60
— dB ²
Full-scale signal input voltage 6.59•VA 6.94•VA 7.29•VA V_PP
Common-mode rejection ratio (217 Hz @ 500 mV_PP) ⁴ —
60
— dB ²
Group delay ⁵ — 7.6/Fs —
s
ISENSE± monitoring
characteristics (IMON)
Data width —
16
— Bits
Dynamic range (unweighted), ISENSE± = ±0.625 A (1.25 A_PP) —
56
— dB ²
Total harmonic distortion, –29.5 dBFS ⁶ —
–45
— dB ²
Full-scale signal input voltage 1.56•VA 1.64•VA 1.72•VA V_PP
VMON-to-IMON isolation ⁷ —
56
— dB ²
Group delay ⁸ — 7.6/Fs —
s
VP monitoring characteristics
Data width —
8
— Bits
Voltage resolution (See the equation in Section 4.8.4.) —
35.3
— mV
(FF code) signal input voltage (VP) 2.89•VA 3.05•VA 3.20•VA V
VPMON = 1011 0011 —
2.8
—
V
VPMON = 1011 0100 — 2.835 —
V
……
…
…
…
VPMON = 1111 1111 — 5.482 —
V
VPMON = 0000 0000 — 5.518 —
V
1.Typical value is specified with PDN_AMP and PDN_xMON bits initially set. Maximum power-up time is affected by the actual MCLK_INT frequency.
2.Parameters given in dB are referred to the applicable typical full-scale voltages. Applies to all THD+N and resolution values in the table
3.VSENSE± THD is measured with the Class D amplifier as the audio source connected to an 8- + 33H speaker load, supplied by a 6.3-V_PP, 1-kHz
sine wave, operating under the typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –3.8-dBFS
VMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing distortion of the signal supplied to VSENSE±
4.CMRR test setup for VSENSE±:
VSENSE+
VSENSE–
217 Hz
500 mV_PP
DC Offset = 0
5.VMON group delay is measured from the time a signal is presented on the VSENSE± and pins until the MSB of the digitized signal exits the serial
port. Fs is the LRCK rate.
6.For reference, injecting a 125-mVpp fully differential sine wave into the ISENSE± pins (equivalent to a ±0.625 A current with a 0.1- ISENSE resistor)
produces an IMON output of –29.5 dBFS (since typical full-scale is 1.64*VA, in V_PP). ISENSE± monitoring THD is measured using the Class D
amplifier as the audio source, which is connected to an 8- + 33-H speaker load, supplied by a 7.0-V_PP, 1-kHz sine wave, operating under the
typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –29.5-dBFS amplitude IMON output. Larger
Class D amplifier amplitudes begin to exhibit clipping behavior, increasing the distortion of the signal supplied to ISENSE±.
7.VMON-to-IMON isolation is the error in the current sense due to VMON, expressed relative to full-scale sense current in decibels.
8.IMON group delay is measured from when a signal is presented on the ISENSE± pins until the MSB of the digitized signal exits the serial port. Fs is
the LRCK rate.
Table 3-8. Digital Interface Specifications and Characteristics
Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = 0 V, T_A = +25°C.
Parameters
Symbol
Test Conditions
Min
Max
Input leakage current (per pin) ^1,2
FLOUT2/AD0 I_IN
FLEN, FLINH, LRCK
——
±7.5
——
±4.5
MCLK, SCLK, SDOUT
SCL, SDA, INT, RESET
——
±4.5
——
±0.1
Input capacitance
VA logic I/Os
I_IN
High-level output voltage V_OH
——
10
I_OH = –67/–100 A ³ VA–0.2 —
Low-level output voltage V_OL
High-level input voltage V_IH
Low-level input voltage V_IL
All outputs, I_OL = 67/100 A ³ —
INT, SDA, IOL = 3 mA —
— 0.70•VA
0.20
0.4
—
— — 0.30•VA
Units
A
A
A
A
pF
V
V
V
V
V
1.Specification includes current through internal pull up/down resistors, where applicable (as defined in Section 1).
2.Leakage current is measured with VA = 1.80 V, VP = 3.60 V, VBST = 3.60 V, and RESET asserted. Each pin is tested while driven high and low.
3.For the ADSP output SDOUT and potential outputs SCLK and LRCK (if M/S = 1), if ADSP_DRIVE = 0 see Section 7.13, I_OH and I_OL are –100 and
+100 A. If ADSP_DRIVE = 1, I_OH and I_OL are –67 and +67 A. For other, non-ADSP_DRIVE-affected outputs, I_OH and I_OLare –100 and +100 A.
DS963F5
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