CS2000-CP Datasheet, PDF (31/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.7 Function Configuration 1 (Address 16h)
7
ClkSkipEn
6
AuxLockCfg
5
Reserved
4
RefClkDiv1
3
RefClkDiv0
2
Reserved
CS2000-CP
1
Reserved
0
Reserved
8.7.1
8.7.2
Clock Skip Enable (ClkSkipEn)
This bit enables clock skipping mode for the PLL and allows the PLL to maintain lock even when the
CLK_IN has missing pulses.
ClkSkipEn
0
1
Application:
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 14
Note: f_{CLK_IN} must be < 80 kHz to use this feature.
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] = 11), this bit configures the
AUX_OUT driver to either push-pull or open drain. It also determines the polarity of the lock signal. If
AUX_OUT is configured as a clock output, the state of this bit is disregarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 22
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
8.7.3
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0]
00
01
10
11
Application:
Reference Clock Input Divider
REF_CLK Frequency Range
÷ 4.
32 MHz to 75 MHz (50 MHz with XTI)
÷ 2.
16 MHz to 37.5 MHz
÷ 1.
8 MHz to 18.75 MHz
Reserved.
“Internal Timing Reference Clock Divider” on page 13
DS761PP1
31