CS2000-CP Datasheet, PDF (27/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
8. REGISTER DESCRIPTIONS
In I²C Mode all registers are read/write unless otherwise stated. In SPI mode all registers are write only. All “Re-
served” registers must maintain their default state to ensure proper functional operation. The default state of each
bit after a power-up sequence or reset is indicated by the shaded row in the bit decode table and in the “Register
Quick Reference” on page 26.
Control port mode is entered when the device recognizes a valid chip address input on its I²C/SPI serial control pins
and the EnDevCfg1 and EnDevCfg2 bits are set to 1.
8.1 Device I.D. and Revision (Address 01h)
7
Device4
6
Device3
5
Device2
4
Device1
3
Device0
2
Revision2
1
Revision1
0
Revision0
8.1.1
Device Identification (Device[4:0]) - Read Only
I.D. code for the CS2000.
Device[4:0]
00000
Device
CS2000.
8.1.2
Device Revision (Revision[2:0]) - Read Only
CS2000 revision level.
REVID[2:0]
100
Revision Level
B2.
8.2 Device Control (Address 02h)
7
Unlock
6
FsDet1
5
FsDet0
4
Reserved
3
Reserved
2
Reserved
1
AuxOutDis
0
ClkOutDis
8.2.1
Unlock Indicator (Unlock) - Read Only
Indicates the lock state of the PLL.
Unlock
0
1
PLL Lock State
PLL is Locked.
PLL is Unlocked.
8.2.2
PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only
Indicates the range of the frequency of CLK_IN relative to the frequency of SysClk. For audio applications,
this can be used to distinguish single-, double-, and quad-speed modes.
FsDet[1:0]
00
01
10
11
Application:
f_SysClk / f_{CLK_IN}
> 224.
96 to 224.
< 96.
Reserved.
“CLK_IN Frequency Detector” on page 14
DS761PP1
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