CS2000-CP Datasheet, PDF (20/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

5.3.6
CS2000-CP
Fractional-N Source Selection
To select between the static ratio based Frequency Synthesizer Mode and the dynamic ratio based Hybrid
PLL Mode, the source for the fractional-N value for the Frequency Synthesizer must be changed. The
Fractional-N value can either be sourced directly from the Effective Ratio (static ratio) or from the output
of the Digital PLL (dynamic ratio) (see Figure 14 on page 21). The setting of this function can be made
manual or automatically depending on the presence of CLK_IN.
5.3.6.1
Manual Fractional-N Source Selection for the Frequency Synthesizer
Manual selection of the fractional-N source for the frequency synthesizer is made by setting the
FracNSrc bit to select the desired ratio source. The LockClk[1:0] bits (even if unused) must be set
to the same value as the RSel[1:0] bits in order to maintain manual selectability of this function (see
Section 5.3.6.2 on page 20).
Referenced Control
Register Location
Rsel[1:0]................................ “Device Configuration 1 (Address 03h)” on page 28
LockClk[1:0] .......................... “Device Configuration 2 (Address 04h)” section on page 29
FracNSrc............................... “Device Configuration 2 (Address 04h)” section on page 29
5.3.6.2
Automatic Fractional-N Source Selection for the Frequency Synthesizer
Automatic source selection allows for the selection of the frequency synthesizer’s fractional-N value
to be made dependent on the presence of the CLK_IN signal. When CLK_IN is present the device
will use the dynamic ratio generated from the Digital PLL and CLK_IN for Hybrid PLL Mode. When
CLK_IN is not present, the device will use RefClk and the static ratio for Frequency Synthesizer
Mode. Before switching to SysClk and re-acquiring lock the CS2000 will wait for 2²³ SysClk cycles
after losing CLK_IN (see “CLK_IN Skipping Mode” on page 14).
The User Defined Ratio pointed to by RSel[1:0] should contain the desired CLK_OUT to RefClk ra-
tio to be used when CLK_IN is not present. The User Defined Ratio pointed to by LockClk[1:0]
should contain the desired CLK_OUT to CLK_IN ratio to be used when CLK_IN is present. Auto-
matic source selection is enabled when the LockClk[1:0] bits are set to point to a different User De-
fined Ratio from the one pointed to by the RSel[1:0] bits.
When automatic source selection is enabled, the FracNSrc bit (used for manual clock selection) will
be ignored.
To disable the automatic source selection feature, set the LockClk[1:0] bits and the RSel[1:0] bits
to the same value. The FracNSrc bit must then be used to select the desired clock used for the
PLL’s frequency reference.
Referenced Control
Register Location
RSel[1:0] ............................... “Ratio Selection (RSel[1:0])” on page 28
LockClk[1:0] .......................... “Lock Clock Ratio (LockClk[1:0])” section on page 29
FracNSrc............................... “Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
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