CS2000-CP Datasheet, PDF (30/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.4.3
Fractional-N Source for Frequency Synthesizer (FracNSrc)
Selects static or dynamic ratio mode when auto clock switching is disabled.
FracNSrc
0
1
Application:
Fractional-N Source Selection
Static Ratio directly from R_EFF for Frequency Synthesizer Mode
Dynamic Ratio from Digital PLL for Hybrid PLL Mode
“Fractional-N Source Selection” on page 20
CS2000-CP
8.5 Global Configuration (Address 05h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Freeze
2
Reserved
1
Reserved
0
EnDevCfg2
8.5.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE
0
1
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
8.5.2
Enable Device Configuration Registers 2 (EnDevCfg2)
This bit, in conjunction with EnDevCfg1, enables control port mode. Both bits must be set to 1 during ini-
tialization.
EnDevCfg2
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
Note: EnDevCfg1 must also be set to enable control port mode (“SPI / I²C Control Port” on page 24).
8.6 Ratio 0 - 3 (Address 06h - 15h)
7
MSB
MSB-8
LSB+15
LSB+7
6
5
4
3
2
1
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0
MSB-7
MSB-15
LSB+8
LSB
These registers contain the User Defined Ratios as shown in the “Register Quick Reference” section on
page 26. Each group of 4 registers forms a single 32-bit ratio value as shown above. See “Output to Input
Frequency Ratio Configuration” on page 17 and “Calculating the User Defined Ratio” on page 33 for more
details.
30
DS761PP1