CS2000-CP Datasheet, PDF (15/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
time listed in the “AC Electrical Characteristics” on page 8 after which lock will be acquired and the PLL
output will resume.
2²³ SysClk cycles
Lock Time
2²³ SysClk cycles
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
Figure 9. CLK_IN removed for > 2²³ SysClk cycles
If CLK_IN is removed and then reapplied within 2²³ SysClk cycles but later than t_CS, the ClkSkipEn bit will
have no effect and the PLL output will continue until CLK_IN is re-applied (see Figure 10). Once CLK_IN
is re-applied, the PLL will go unlocked only for the time it takes to acquire lock; the PLL_OUT state will be
determined by the ClkOutUnl bit during this time.
2²³ SysClk cycles
tCS
Lock Time
2²³ SysClk cycles
tCS
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=0 or 1
ClkOutUnl=0
PLL_OUT
ClkSkipEn=0 or 1
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
= invalid clocks
Figure 10. CLK_IN removed for < 2²³ SysClk cycles but > t_CS
If CLK_IN is removed and then re-applied within t_CS, the ClkSkipEn bit determines whether PLL_OUT
continues while the PLL re-acquires lock (see Figure 11). When ClkSkipEn is disabled and CLK_IN is re-
moved the PLL output will continue until CLK_IN is re-applied at which point the PLL will go unlocked only
for the time it takes to acquire lock; the PLL_OUT state will be determined by the ClkOutUnl bit during this
time. When ClkSkipEn is enabled and CLK_IN is removed the PLL output clock will remain continuous
throughout the missing CLK_IN period including the time while the PLL re-acquires lock.
tCS
tCS
Lock Time
CLK_IN
CLK_IN
ClkSkipEn=1
ClkOutUnl=0 or 1
PLL_OUT
ClkSkipEn=0
ClkOutUnl=1
PLL_OUT
UNLOCK
UNLOCK
CLK_IN
tCS
Lock Time
= invalid clocks
ClkSkipEn=0
ClkOutUnl=0
PLL_OUT
UNLOCK
Figure 11. CLK_IN removed for < t_CS
Referenced Control
Register Location
ClkSkipEn..............................“Clock Skip Enable (ClkSkipEn)” on page 31
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32
DS761PP1
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