CS2000-CP Datasheet, PDF (29/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.3.3
CS2000-CP
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
00
01
10
11
Application:
Auxiliary Output Source
RefClk.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 22
Note: When set to 11, AuxLckCfg sets the polarity and driver type (“AUX PLL Lock Output Configura-
tion (AuxLockCfg)” on page 31).
8.3.4
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, enables control port mode. Both bits must be set to 1 during ini-
tialization.
EnDevCfg1
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
Note: EnDevCfg2 must also be set to enable control port mode (“SPI / I²C Control Port” on page 24).
8.4 Device Configuration 2 (Address 04h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
AutoRMod
2
LockClk1
1
LockClk0
0
FracNSrc
8.4.1
Auto R-Modifier Enable (AutoRMod)
Controls the automatic ratio modifier function.
AutoRMod
0
1
Application:
Automatic R-Mod State
Disabled.
Enabled.
“Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only” on page 18
8.4.2
Lock Clock Ratio (LockClk[1:0])
Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.
LockClk[1:0]
00
01
10
11
Application:
CLK_IN Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
Section 5.3.2 on page 17
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