CS2000-CP Datasheet, PDF (18/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

5.3.3
CS2000-CP
Manual Ratio Modifier (R-Mod)
The manual Ratio Modifier is used to internally multiply/divide the currently addressed R_UD (the Ratio_0-3
stored in the register space remain unchanged). The available options for R_MOD are summarized in
Table 2 on page 18.
The R-Mod value selected by RModSel[2:0] is always used in the calculation for the Effective Ratio
(R_EFF), see “Effective Ratio (REFF)” on page 19. If R-Mod is not desired, RModSel[2:0] should be left at
its default value of ‘000’, which corresponds to an R-Mod value of 1, thereby effectively disabling the ratio
modifier.
RModSel[2:0]
000
001
010
011
100
101
110
111
Ratio Modifier
1
2
4
8
0.5
0.25
0.125
0.0625
Table 2. Ratio Modifier
Referenced Control
Register Location
Ratio_0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 28
5.3.4
Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only
The Automatic R-Modifier uses the status of the CLK_IN Frequency Range Indicator (see section 5.2.1
on page 14) to implement a frequency dependent multiply of the currently addressed R_UD as shown in
Table 3.
Like with R-Mod, the Ratio_0-3 stored in the register space remain unchanged. The Automatic Ratio-Mod-
ifier is enabled by the AutoRMod bit.
FsDetect[1:0]
00
01
10
f_SysClk / f_{CLK_IN}
> 224
96 - 224
< 96
Auto R Modifier
1
0.5
0.25
Table 3. Automatic Ratio Modifier
It is important to note that Auto R-Mod (if enabled) is applied in addition to any R-Mod already selected
by the RModSel[2:0] bits and is used to calculate the Effective Ratio (see Section 5.3.5 on page 19).
Auto R-Mod can be used to generate the appropriate oversampling clock (MCLK) for audio A/D and D/A
converters. For example, if the clock applied to CLK_IN is the audio sample rate, Fs (also known as the
word, frame or Left/Right clock), and SysClk is 12.288 MHz (REF_CLK = 12.288 MHz with RefClkDiv[1:0]
18
DS761PP1