CS2000-CP Datasheet, PDF (21/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
5.3.7 Ratio Configuration Summary
The R_UD is the user defined ratio for which up to four different values (Ratio_0-3) can be stored in the reg-
ister space. The RSel[1:0] or LockClk[1:0] bits then select the user defined ratio to be used (depending
on if static or dynamic ratio mode is to be used). The resolution for the R_UD is selectable, for the dynamic
ratio mode, by setting LFRatioCfg. R-Mods can be applied to both modes whereas Auto R-Mod is only
available in dynamic mode. The user defined ratio, ratio modifier, and automatic ratio modifier make up
the effective ratio R_EFF, the final calculation used to determine the output to input clock ratio. The effective
ratio is then corrected for the internal dividers. The frequency synthesizer’s fractional-N source selection
is made between the static ratio (in frequency synthesizer mode) or the dynamic ratio generated from the
digital PLL (in Hybrid PLL mode) by either the FracNSrc bit for manual mode or the presence of CLK_IN
in automatic mode. The conceptual diagram in Figure 14 summarizes the features involved in the calcu-
lation of the ratio values used to generate the fractional-N value which controls the Frequency Synthesiz-
er.
Timing Reference Clock
RSel[1:0] =? LockClk[1:0]
(XTI/REF_CLK)
Effective Ratio REFF
RSel[1:0]
User Defined Ratio RUD
Ratio 0
Ratio 1
Ratio 2
Ratio 3
Ratio Format
12.20
only
RModSel[2:0]
Ratio
Modifier
CLK_IN sense
(auto selection)
≠
FracNSrc
(manual selection)
=
Divide
RefClkDiv[1:0]
R Correction
Static Ratio
Dynamic Ratio
CLK_IN not present
or FracNSrc=0
SysClk
N
CLK_IN present
or FracNSrc=1
RefClkDiv[1:0]
Frequency
Synthesizer
PLL Output
12.20
20.12
LockClk[1:0]
LFRatioCfg
Ratio
Modifier
Auto
R-Mod
R Correction
Digital PLL &
Fractional N Logic
AutoRMod
FsDet[1:0]
Frequency Reference Clock
(CLK_IN)
Figure 14. Ratio Feature Summary
Referenced Control
Register Location
Ratio_0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
RSel[1:0] ...............................“Ratio Selection (RSel[1:0])” on page 28
LockClk[1:0] ..........................“Lock Clock Ratio (LockClk[1:0])” section on page 29
LFRatioCfg ............................“Low-Frequency Ratio Configuration (LFRatioCfg)” on page 32
RModSel[2:0] ........................“R-Mod Selection (RModSel[2:0])” section on page 28
AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 29
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 27
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 31
FracNSrc ...............................“Fractional-N Source for Frequency Synthesizer (FracNSrc)” section on page 30
DS761PP1
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