CS2000-CP Datasheet, PDF (2/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

CS2000-CP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 5
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 6
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 7
RECOMMENDED OPERATING CONDITIONS .................................................................................... 7
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 7
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 8
CONTROL PORT SWITCHING CHARACTERISTICS- I²C FORMAT ................................................... 9
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT ............................................... 10
4. ARCHITECTURE OVERVIEW ............................................................................................................. 11
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ......................................................................... 11
4.2 Hybrid Analog-Digital Phase Locked Loop .................................................................................... 11
4.2.1 Fractional-N Source Selection for the Frequency Synthesizer .............................................. 12
5. APPLICATIONS ................................................................................................................................... 13
5.1 Timing Reference Clock Input ........................................................................................................ 13
5.1.1 Internal Timing Reference Clock Divider ............................................................................... 13
5.1.2 Crystal Connections (XTI and XTO) ...................................................................................... 13
5.1.3 External Reference Clock (REF_CLK) .................................................................................. 14
5.2 Frequency Reference Clock Input, CLK_IN ................................................................................... 14
5.2.1 CLK_IN Frequency Detector ................................................................................................. 14
5.2.2 CLK_IN Skipping Mode ......................................................................................................... 14
5.2.3 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 16
5.3 Output to Input Frequency Ratio Configuration ............................................................................. 17
5.3.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 17
5.3.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 17
5.3.3 Manual Ratio Modifier (R-Mod) ............................................................................................. 18
5.3.4 Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only ......................................... 18
5.3.5 Effective Ratio (REFF) .......................................................................................................... 19
5.3.6 Fractional-N Source Selection ............................................................................................... 20
5.3.7 Ratio Configuration Summary ............................................................................................... 21
5.4 PLL Clock Output ........................................................................................................................... 22
5.5 Auxiliary Output .............................................................................................................................. 22
5.6 Clock Output Stability Considerations ............................................................................................ 23
5.6.1 Output Switching ................................................................................................................... 23
5.6.2 PLL Unlock Conditions .......................................................................................................... 23
6. SPI / I²C CONTROL PORT ................................................................................................................... 24
6.1 SPI Control ..................................................................................................................................... 24
6.2 I²C Control ...................................................................................................................................... 24
6.3 Memory Address Pointer ............................................................................................................... 26
6.3.1 Map Auto Increment .............................................................................................................. 26
7. REGISTER QUICK REFERENCE ........................................................................................................ 26
8. REGISTER DESCRIPTIONS ................................................................................................................ 27
8.1 Device I.D. and Revision (Address 01h) ....................................................................................... 27
8.1.1 Device Identification (Device[4:0]) - Read Only ..................................................................... 27
8.1.2 Device Revision (Revision[2:0]) - Read Only ........................................................................ 27
8.2 Device Control (Address 02h) ........................................................................................................ 27
8.2.1 Unlock Indicator (Unlock) - Read Only .................................................................................. 27
8.2.2 PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only .................................................. 27
8.2.3 Auxiliary Output Disable (AuxOutDis) ................................................................................... 28
8.2.4 PLL Clock Output Disable (ClkOutDis) .................................................................................. 28
8.3 Device Configuration 1 (Address 03h) ........................................................................................... 28
8.3.1 R-Mod Selection (RModSel[2:0]) ........................................................................................... 28
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DS761PP1