AT91SAM9G45PRE Datasheet, PDF (947/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

AT91SAM9G45
5. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1
and TSADCC_LCDR.
6. If Channel 2 is enabled, convert Channel 2 and store result in both TSADCC_CDR2
and TSADCC_LCDR.
7. If Channel 3 is enabled, convert Channel 3 and store result in both TSADCC_CDR3
and TSADCC_LCDR.
8. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
responding TSADCC_CDRx and TSADCC_LCDR.
9. If SLEEP is set, sleep down the ADC cell.
If the PDC is enabled, all the converted data are transferred contiguously in the memory buffer.
The bit LOWRES defines which resolution is used, either 8-bit or 10-bit, and thus the width of the
PDC memory buffer.
40.10.2
Touch Screen Mode
Writing TSAMOD to “Touch Screen Only Mode” automatically enables the touch screen pins as
analog inputs, and thus disables the digital function of the corresponding pins.
In Touch Screen Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are auto-
matically activated and the bits CH0 to CH3 are automatically set in the “TSADCC Channel
Status Register”.
The remaining channels can be either enabled or disabled by the user and their conversions are
performed at the end of each touch screen sequence.
The resolution is forced to 10 bits, regardless of the LOWRES bit setting.
At each trigger, if the bit PRES in “TSADCC Mode Register” is disabled, the following sequence
is performed to measure only position.
1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time.
2. Close the switches on the inputs X_P and X_M during the Sample and Hold Time.
3. Convert Channel X_M and store the result in TSADCC_CDR1.
4. Close the switches on the inputs X_P and X_M during the Sample and Hold Time.
5. Convert Channel X_P, subtract TSADCC_CDR1 from the result and store the subtraction
result in both TSADCC_CDR0 and TSADCC_LCDR.
6. Close the switches on the inputs X_P and X_M during the Sample and Hold Time.
7. Convert Channel Y_P, subtract TSADCC_CDR1 from the result and store the subtraction
result in both TSADCC_CDR1 and TSADCC_LCDR.
8. Close the switches on the inputs Y_P and Y_M during the Sample and Hold Time.
9. Convert Channel Y_M and store the result in TSADCC_CDR3.
10. Close the switches on the inputs Y_P and Y_M during the Sample and Hold Time.
11. Convert Channel Y_P, subtract TSADCC_CDR3 from the result and store the subtraction
result in both TSADCC_CDR2 and TSADCC_LCDR.
12. Close the switches on the inputs Y_P and Y_M during the Sample and Hold Time.
13. Convert Channel X_P, subtract TSADCC_CDR3 from the result and store the subtraction
result in both TSADCC_CDR3 and TSADCC_LCDR.
14. If Channel 4 to Channel 7 are enabled, convert the Channels and store result in the cor-
responding TSADCC_CDRx and TSADCC_LCDR.
15. If SLEEP is set, sleep down the ADC cell.
The resulting buffer is 16 bits wide and its structure stored in memory is:
6438F–ATARM–21-Jun-10
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