AT91SAM9G45PRE Datasheet, PDF (72/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

12.4 Functional Description
12.4.1
Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State
Manager. It runs at Slow Clock and generates the following reset signals:
• proc_nreset: Processor reset line. It also resets the Watchdog Timer.
• backup_nreset: Affects all the peripherals powered by VDDBU.
• periph_nreset: Affects the whole set of embedded peripherals.
• nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on soft-
ware action. The Reset State Manager controls the generation of reset signals and provides a
signal to the NRST Manager when an assertion of the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling
external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by
the crystal oscillator startup time maximum value that can be found in the section Crystal Oscil-
lator Characteristics in the Electrical Characteristics section of the product documentation.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Con-
troller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.
12.4.2
NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager. Figure 12-2 shows the block diagram of the NRST Manager.
Figure 12-2. NRST Manager
NRST
RSTC_SR
URSTS
NRSTL
RSTC_MR
URSTIEN
RSTC_MR
URSTEN
Other
interrupt
sources
RSTC_MR
ERSTL
nrst_out _{External Reset Timer}
rstc_irq
user_reset
exter_nreset
12.4.2.1
NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low,
a User Reset is reported to the Reset State Manager.
However, the NRST Manager can be programmed to not trigger a reset when an assertion of
NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.
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