AT91SAM9G45PRE Datasheet, PDF (889/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

38.6.20 UDPHS DMA Channel Address Register
Name:
UDPHS_DMAADDRESSx [x = 1..5]
Addresses:
0xFFF78324 [1], 0xFFF78334 [2], 0xFFF78344 [3], 0xFFF78354 [4], 0xFFF78364 [5]
Access Type:
Read-write
31
30
29
28
27
26
25
24
BUFF_ADD
23
22
21
20
19
18
17
16
BUFF_ADD
15
14
13
12
11
10
9
8
BUFF_ADD
7
6
5
4
3
2
1
0
BUFF_ADD
• BUFF_ADD
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access
byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word
boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel
buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either
determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register
END_TR_EN bit is set.
889 AT91SAM9G45
6438F–ATARM–21-Jun-10