AT91SAM9G45PRE Datasheet, PDF (1101/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

Figure 45-2. Datapath Structure
Input Interface
FIFO
AT91SAM9G45
Serializer
Palette
Dithering
Configuration IF
Control Interface
Output
Shifter
Output Interface
This module transforms the data read from the memory into a format according to the LCD mod-
ule used. It has four different interfaces: the input interface, the output interface, the
configuration interface and the control interface.
• The input interface connects the datapath with the DMA controller. It is a dual FIFO interface
with a data bus and two push lines that are used by the DMA controller to fill the FIFOs.
• The output interface is a 24-bit data bus. The configuration of this interface depends on the
type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface).
• The configuration interface connects the datapath with the configuration block. It is used to
select between the different datapath configurations.
• The control interface connects the datapath with the timing generation block. The main
control signal is the data-request signal, used by the timing generation module to request
new data from the datapath.
The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The
parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data
is available at the output of the datapath. The parameter cycles_per_data is the minimum num-
ber of LCDC Core clock cycles between two consecutive data at the output interface.
6438F–ATARM–21-Jun-10
1101