AT91SAM9G45PRE Datasheet, PDF (114/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

15.5.1 Periodic Interval Timer Mode Register
Register Name:
PIT_MR
Address:
0xFFFFFD30
Access Type:
Read/Write
31
30
29
28
27
26
25
24
–
–
–
–
–
–
PITIEN
PITEN
23
22
21
20
19
18
17
16
–
–
–
–
PIV
15
14
13
12
11
10
9
8
PIV
7
6
5
4
3
2
1
0
PIV
• PIV: Periodic Interval Value
Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to
(PIV + 1).
• PITEN: Period Interval Timer Enabled
0 = The Periodic Interval Timer is disabled when the PIV value is reached.
1 = The Periodic Interval Timer is enabled.
• PITIEN: Periodic Interval Timer Interrupt Enable
0 = The bit PITS in PIT_SR has no effect on interrupt.
1 = The bit PITS in PIT_SR asserts interrupt.
114 AT91SAM9G45
6438F–ATARM–21-Jun-10