AT91SAM9G45PRE Datasheet, PDF (689/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

AT91SAM9G45
34.9.6 SSC Transmit Frame Mode Register
Name:
SSC_TFMR
Addresses:
0xFFF9C01C (0), 0xFFFA001C (1)
Access:
Read-write
31
30
29
28
27
26
25
24
FSLEN_EXT FSLEN_EXT FSLEN_EXT FSLEN_EXT
–
–
–
FSEDGE
23
22
FSDEN
21
20
FSOS
19
18
17
16
FSLEN
15
14
13
12
11
10
9
8
–
–
–
–
DATNB
7
MSBF
6
5
4
–
DATDEF
3
2
1
0
DATLEN
• DATLEN: Data Length
0 = Forbidden value (1-bit data length not supported).
Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the
PDC assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15
(included), half-words are transferred, and for any other value, 32-bit words are transferred.
• DATDEF: Data Default Value
This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the
PIO Controller, the pin is enabled only if the SCC TD output is 1.
• MSBF: Most Significant Bit First
0 = The lowest significant bit of the data register is shifted out first in the bit stream.
1 = The most significant bit of the data register is shifted out first in the bit stream.
• DATNB: Data Number per frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1).
• FSLEN: Transmit Frame Syn Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync
Data Register if FSDEN is 1.
This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal.
Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period.
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