AT91SAM9G45PRE Datasheet, PDF (613/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

AT91SAM9G45
The PDC uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDC
always writes in the Transmit Holding register (US_THR) and it always reads in the Receive
Holding register (US_RHR). The size of the data written or read by the PDC in the USART is
always a byte.
33.7.8.23
Master Node Configuration
The user can choose between two PDC modes by the PDCM bit in the LIN Mode register
(US_LINMR):
• PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDC in
the Transmit Holding register US_THR (instead of the LIN Mode register US_LINMR).
Because the PDC transfer size is limited to a byte, the transfer is split into two accesses.
During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are
written. During the second access the 8-bit DLC field is written.
• PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by
the user in the LIN Mode register (US_LINMR).
The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response
(NACT = PUBLISH).
The READ buffer contains the DATA if the USART receives the response (NACT =
SUBSCRIBE).
Figure 33-52. Master Node with PDC (PDCM=1)
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
WRITE BUFFER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
PDC
(DMA)
DLC
NODE ACTION = PUBLISH
APB bus
IDENTIFIER
RXRDY
USART3
LIN CONTROLLER
READ BUFFER
DATA 0
PDC
(DMA)
NODE ACTION = SUBSCRIBE
APB bus
RXRDY
USART3
LIN CONTROLLER
TXRDY
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DATA N
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DATA N
6438F–ATARM–21-Jun-10
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