AT91SAM9G45PRE Datasheet, PDF (199/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

Figure 21-15. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NCS
D[31:0]
AT91SAM9G45
21.8.5
Coding Timing Parameters
All timing parameters are defined for one chip select and are grouped together in one
SMC_REGISTER according to their type.
The SMC_SETUP register groups the definition of all setup parameters:
• NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP
The SMC_PULSE register groups the definition of all pulse parameters:
• NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE
The SMC_CYCLE register groups the definition of all cycle parameters:
• NRD_CYCLE, NWE_CYCLE
Table 21-4 shows how the timing parameters are coded and their permitted range.
Table 21-4. Coding and Range of Timing Parameters
Coded Value
setup [5:0]
pulse [6:0]
cycle [8:0]
Number of Bits
6
7
Effective Value
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
9
256 x cycle[8:7] + cycle[6:0]
Permitted Range
Coded Value
Effective Value
0 ≤ ≤ 31
0 ≤ ≤ 128+31
0 ≤ ≤ 63
0 ≤ ≤ 256+63
0 ≤ ≤ 127
0 ≤ ≤ 256+127
0 ≤ ≤ 512+127
0 ≤ ≤ 768+127
21.8.6
Reset Values of Timing Parameters
Table 21-8 gives the default value of timing parameters at reset.
6438F–ATARM–21-Jun-10
199