AT91SAM9G45PRE Datasheet, PDF (1146/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR

AT91SAM9G45
45.12.26 Contrast Control Register
Name: CONTRAST_CTR
Address:0x00500840
Access: Read-write
Reset value: 0x00000000
31
30
29
–
–
–
23
22
21
–
–
–
15
14
13
–
–
–
7
6
5
–
–
–
28
27
26
25
24
–
–
–
–
–
20
19
18
17
16
–
–
–
–
–
12
11
10
9
8
–
–
–
–
–
4
3
2
1
0
–
ENA
POL
PS
• PS
This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows:
PS
0
0
0
1
1
0
1
1
The counter advances at a rate of fCOUNTER = fLCDC_CLOCK.
The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/2.
The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/4.
The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/8.
• POL
This bit defines the polarity of the output. If 1, the output pulses are high level (the output will be high whenever the value in
the counter is less than the value in the compare register CONSTRAST_VAL). If 0, the output pulses are low level.
• ENA
When 1, this bit enables the operation of the PWM generator. When 0, the PWM counter is stopped.
6438F–ATARM–21-Jun-10
1146