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| AT91SAM9G45PRE Datasheet, PDF (344/1218 Pages) ATMEL Corporation – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR | |||
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26.9 Advanced Interrupt Controller (AIC) User Interface
26.9.1 Base Address
The AIC is mapped at the address 0xFFFF F000. It has a total 4-KByte addressing space. This permits the vectoring fea-
ture, as the PC-relative load/store instructions of the ARM processor support only a ± 4-KByte offset.
Table 26-3. Register Mapping
Offset
0x00
0x04
---
0x7C
0x80
0x84
---
0xFC
0x100
0x104
0x108
0x10C
0x110
0x114
0x118 - 0x11C
0x120
0x124
0x128
0x12C
0x130
0x134
0x138
0x13C
0x140
0x144
0x148
0x14C - 0x1E0
0x1EC - 0x1FC
Register
Source Mode Register 0
Source Mode Register 1
---
Source Mode Register 31
Source Vector Register 0
Source Vector Register 1
---
Source Vector Register 31
Interrupt Vector Register
FIQ Interrupt Vector Register
Interrupt Status Register
Interrupt Pending Register(2)
Interrupt Mask Register(2)
Core Interrupt Status Register
Reserved
Interrupt Enable Command Register(2)
Interrupt Disable Command Register(2)
Interrupt Clear Command Register(2)
Interrupt Set Command Register(2)
End of Interrupt Command Register
Spurious Interrupt Vector Register
Debug Control Register
Reserved
Fast Forcing Enable Register(2)
Fast Forcing Disable Register(2)
Fast Forcing Status Register(2)
Reserved
Reserved
Name
AIC_SMR0
AIC_SMR1
---
AIC_SMR31
AIC_SVR0
AIC_SVR1
---
AIC_SVR31
AIC_IVR
AIC_FVR
AIC_ISR
AIC_IPR
AIC_IMR
AIC_CISR
---
AIC_IECR
AIC_IDCR
AIC_ICCR
AIC_ISCR
AIC_EOICR
AIC_SPU
AIC_DCR
---
AIC_FFER
AIC_FFDR
AIC_FFSR
---
Access
Read-write
Read-write
---
Read-write
Read-write
Read-write
---
Read-write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
---
Write-only
Write-only
Write-only
Write-only
Write-only
Read-write
Read-write
---
Write-only
Write-only
Read-only
---
Reset
0x0
0x0
---
0x0
0x0
0x0
---
0x0
0x0
0x0
0x0
0x0(1)
0x0
0x0
---
---
---
---
---
---
0x0
0x0
---
---
---
0x0
---
Notes:
1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset,
thus not pending.
2. PID2...PID31 bit fields refer to the identifiers as defined in the Peripheral Identifiers Section of the product datasheet.
3. Values in the Version Register vary with the version of the IP block implementation.
344 AT91SAM9G45
6438FâATARMâ21-Jun-10
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