XMEGAA_09 Datasheet, PDF (73/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
6.8.2
CHnCTRL – Event Channel n Control Register
.
Bit
7
-
Read/Write
R
Initial Value
0
6
5
QDIRM[1:0]
R/W
R/W
0
0
4
QDIEN
R/W
0
3
QDEN
R/W
0
2
1
0
DIGFILT[2:0]
R/W
R/W
R
0
0
0
CHnCTRL
• Bit 7 - Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
• Bit 6:5 - QDIRM[1:0]: Quadrature Decode Index Recognition Mode
These bits determine the quadrature state for the QDPH0 and QDPH90 signals where a valid
index signal is recognized and the counter index data event is given according to Table 6-5 on
page 73. These bits is only needed to set when a quadrature encoed with a connected index sig-
nal is used.
These bits are only available for CH0CTRL, CH2CTRL and CH4CTRL
Table 6-5. QDIRM Bit Settings
QDIRM[1:0] Index Recognition State
0
0 {QDPH0, QDPH90} = 0b00
0
1 {QDPH0, QDPH90} = 0b01
1
0 {QDPH0, QDPH90} = 0b10
1
1 {QDPH0, QDPH90} = 0b11
• Bit 4 - QDIEN: Quadrature Decode Index Enable
When this bit is set the event channel will be used as QDEC index source, and the index data
event will be enabled.
These bit is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 3 - QDEN: Quadrature Decode Enable
Setting this bit enables QDEC operation.
These bits is only available for CH0CTRL, CH2CTRL and CH4CTRL.
• Bit 2:0 - DIGFILT[2:0]: Digital Filter Coefficient
These bits define the length of digital filtering used. Events will be passed through to the event
channel only when the event source has been active and sampled with the same level for a a
number of peripheral clock for the number of cycles as defined by DIGFILT.
73
8077H–AVR–12/09