XMEGAA_09 Datasheet, PDF (27/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
4.15.8 CTRLA - Non-Volatile Memory Control Register A
Bit
+0x0B
Read/Write
Initial Value
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
CMDEX
CTRLA
R
R
R
R
R
R
R
S
0
0
0
0
0
0
0
0
• Bit 7:1 - Reserved Bits
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - CMDEX: Non-Volatile Memory Command Execute
Setting this bit will execute the command in the CMD register. This bit is protected by the Config-
uration Change Protection (CCP) mechanism, refer to Section 3.12 ”Configuration Change
Protection” on page 12 for details on the CCP.
4.15.9 CTRLB - Non-Volatile Memory Control Register B
Bit
+0x0C
Read/Write
Initial Value
7
6
5
4
3
2
-
-
-
-
EEMAPEN
FPRM
R
R
R
R
R/W
R/W
0
0
0
0
0
0
1
EPRM
R/W
0
0
SPMLOCK
R/W
0
CTRLB
• Bit 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3 - EEMAPEN: EEPROM Data Memory Mapping Enable
Setting this bit will enable Data Memory Mapping of the EEPROM section. The EEPROM can
then be accessed using Load and Store instructions.
• Bit 2 - FPRM: Flash Power Reduction Mode
Setting this bit will enable power saving for the flash memory. The section not being accessed
will be turned off like in sleep mode. If code is running from Application Section, the Boot Loader
Section will be turned off and vice versa. If access to the section that is turned off is required, the
CPU will be halted equally long to the start-up time from the Idle sleep mode.
• Bit 1 - EPRM: EEPROM Power Reduction Mode
Setting this bit will enable power saving for the EEPROM memory. The EEPROM will then be
powered down equal to entering sleep mode. If access is required, the bus master will be halted
equally long as the start-up time from Idle sleep mode.
• Bit 0 - SPMLOCK: SPM Locked
The SPM Locked bit can be written to prevent all further self-programming. The bit is cleared at
reset and cannot be cleared from software. This bit is protected by the Configuration Change
Protection (CCP) mechanism, refer to Section 3.12 ”Configuration Change Protection” on page
12 for details on the CCP.
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