XMEGAA_09 Datasheet, PDF (298/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
Figure 25-14. ADC timing for one single conversion with gain
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9
CLKADC
START
GAINSTAGE SAMPLE
GAINSTAGE AMPLIFY
ADC SAMPLE
IF
CONVERTING BIT
MSB 10 9
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5
4
3
2
1 LSB
25.9.3
Single conversions on two ADC channels
Figure 25-15 on page 298 shows the ADC timing for single conversions on two ADC channels.
The pipelined design enables the second conversion to start on the next ADC clock cycle after t
the first conversion is started. In this example both conversions is triggered at the same time, but
for ADC Channel 1 (CH1) the actual start is not until the ADC sample and conversion of the MSB
for ADC Channel 0 (CH0) is done.
Figure 25-15. ADC timing for single conversions on two ADC channels
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CLKADC
START CH0
START CH1
ADC SAMPLE
IF CH0
IF CH1
CONVERTING BIT CH0
MSB 10
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3
2
1 LSB
CONVERTING BIT CH1
MSB 10
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5
4
3
2
1 LSB
25.9.4
Single conversions on two ADC channels, CH0 with gain
Figure 25-16 on page 299 shows the conversion timing for single conversions on two ADC chan-
nels where ADC Channel 0 uses the gain stage. As the gain stage introduce one addition cycle
for the gain sample and amplify, the sample for ADC Channel 1 is also delayed one ADC clock
cycle, until the ADC sample and MSB conversion is done for ADC Channel 0.
8077H–AVR–12/09
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