XMEGAA_09 Datasheet, PDF (217/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
19.8 Register Description - TWI
19.8.1 CTRL– TWI Common Control Register
Bit
7
6
5
4
3
2
1
0
+0x00
-
-
-
-
-
-
SDAHOLD
EDIEN
CTRL
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:2 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 1 - SDAHOLD: SDA Hold Time Enable.
Setting this bit to one enables an internal hold time on SDA with respect to the negative edge of
SCL.
• Bit 0 - EDIEN: External Driver Interface Enable
Setting this bit enables the use of the external driver interface, clearing this bit enables normal
two wire mode. See Table 19-1 for details.
Table 19-1. External Driver Interface Enable
EDIEN Mode
Comment
Two pin interface,
0
Normal TWI
Slew rate control and input filter.
1
External Driver
Interface
Four pin interface,
Standard I/O, no slew-rate control, no input filter.
19.9 Register Description - TWI Master
19.9.1 CTRLA - TWI Master Control Register A
Bit
7
6
5
4
3
2
1
0
+0x00
INTLVL[1:0]
RIEN
WIEN
ENABLE
-
-
-
CTRLA
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:6 - INTLVL[1:0]: Interrupt Level
The Interrupt Level (INTLVL) bit select the interrupt level for the TWI master interrupts.
• Bit 5 - RIEN: Read Interrupt Enable
Setting the Read Interrupt Enable (RIEN) bit enables the Read Interrupt when the Read Interrupt
Flag (RIF) in the STATUS register is set. In addition the INTLVL bits must be unequal zero for
TWI master interrupts to be generated.
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