XMEGAA_09 Datasheet, PDF (357/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
Figure 29-14. PDI instruction set summary
Cmd
Size A
Size B
LDS
0000
STS
0100
Cmd
Ptr
LD
0010
ST
0110
Size A/B
LDCS 1 0 0 0
STCS _{1 1 0 0}
CS Address
REPEAT _{1 0 1 0 0 0}
Size B
KEY _{1 1 1 0 0 0 0 0}
Cmd
0 0 0 LDS
0 0 1 LD
0 1 0 STS
0 1 1 ST
1 0 0 LDCS (LDS Control/Status)
1 0 1 REPEAT
1 1 0 STCS (STS Control/Status)
1 1 1 KEY
Size A - Address size (direct access)
0 0 Byte
0 1 Word (2 Bytes)
1 0 3 Bytes
1 1 Long (4 Bytes)
Ptr - Pointer access (indirect access)
0 0 *(ptr)
0 1 *(ptr++)
1 0 ptr
1 1 ptr++ - Reserved
Size B - Data size
0 0 Byte
0 1 Word (2 Bytes)
1 0 3 Bytes
1 1 Long (4 Bytes)
CS Address (CS - Control/Status reg.)
0 0 0 0 Register 0
0 0 0 1 Register 1
0 0 1 0 Register 2
0 0 1 1 Reserved
......
1 1 1 1 Reserved
29.6 Register Description - PDI Instruction and Addressing Registers
These registers are all internal registers that are involved in instruction decoding or PDIBUS
addressing. None of these registers are accessible as register in a register space.
29.6.1
Instruction Register
When an instruction is successfully shifted into the physical layer shift-register, it is copied into
the Instruction Register. The instruction is retained until another instruction is loaded. The rea-
son for this is that the REPEAT command may force the same instruction to be run repeatedly
requiring command decoding to be performed several times on the same instruction.
29.6.2
Pointer Register
The Pointer Register is used to store an address value specifying locations within the PDIBUS
address space. During direct data access, the Pointer Register is updated by the specified num-
ber of address bytes given as operand bytes to the instruction. During indirect data access,
addressing is based on an address already stored in the Pointer Register prior to the access
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