XMEGAA_09 Datasheet, PDF (253/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
2. See ”USART” on page 235 for full description of the Master SPI Mode (MSPIM) operation.
• Bits 5:4 - PMODE[1:0]: Parity Mode
These bits enable and set the type of parity generation according to Table 21-7 on page 253.
When enabled, the Transmitter will automatically generate and send the parity of the transmitted
data bits within each frame. The Receiver will generate a parity value for the incoming data and
compare it to the PMODE setting and if a mismatch is detected, the PERR flag in STATUS will
be set.
These bits are unused in Master SPI mode of operation.
Table 21-7. PMODE Bits Settings
PMODE[1:0]
Group Configuration
00
DISABLED
01
10
EVEN
11
ODD
Parity mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
• Bit 3 - SBMODE: Stop Bit Mode
This bit selects the number of stop bits to be inserted by the Transmitter according to Table 21-8
on page 253. The Receiver ignores this setting.
This bit is unused in Master SPI mode of operation.
Table 21-8.
SBMODE Bit Settings
SBMODE
0
1
Stop Bit(s)
1-bit
2-bit
• Bit 2:0 - CHSIZE[2:0]: Character Size
The CHSIZE[2:0] bits sets the number of data bits in a frame according to Table 21-9 on page
253. The Receiver and Transmitter use the same setting.
Table 21-9. CHSIZE Bits Settings
CHSIZE[2:0]
Group Configuration
000
5BIT
001
6BIT
010
7BIT
011
8BIT
100
101
110
111
9BIT
Character size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
8077H–AVR–12/09
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