XMEGAA_09 Datasheet, PDF (186/445 Pages) ATMEL Corporation – Interrupts and Programmable Multi-level Interrupt Controller

XMEGA A
15.7.10 DTHSBUF - Dead-Time High Side Buffer Register
Bit
7
6
5
4
3
2
1
0
+0x0B
DTHSBUF[7:0]
DTHSBUF
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 7:0 - DTHSBUF: Dead-Time High Side Buffer
This register is the buffer for the DTHS Register. If double buffering is used, valid contents in this
register is copied to the DTHS Register on an UPDATE condition.
15.7.11 OUTOVEN - Output Override Enable Register
Bit
+0x0C
Read/Write
Initial Value
7
R/W⁽¹⁾
0
6
R/W⁽¹⁾
0
5
R/W⁽¹⁾
0
4
3
OUTOVEN[7:0]
R/W⁽¹⁾
R/W⁽¹⁾
0
0
2
R/W⁽¹⁾
0
Note: 1. Can only be written if the fault detect flag (FDF) is zero.
1
R/W⁽¹⁾
0
0
R/W⁽¹⁾
0
OUTOVEN
• Bit 7:0 - OUTOVEN[7:0]: Output Override Enable
These bits enable override of corresponding port output register (i.e. one-to-one bit relation to
pin position). The port direction is not overridden
8077H–AVR–12/09
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