EP2AGX190FF35C4N Datasheet, PDF (78/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum

1–70
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–60 lists the DQS phase shift error for Arria II GX devices.
Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Arria II GX
Devices (Note 1)
Number of DQS Delay Buffer
C4
I3, C5, I5
C6
Unit
1
26
30
36
ps
2
52
60
72
ps
3
78
90
108
ps
4
104
120
144
ps
Note to Table 1–60:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a C4 speed grade is ± 78 ps or ± 39 ps.
Table 1–61 lists the DQS phase shift error for Arria II GZ devices.
Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (t_{DQS_PSERR}) for Arria II GZ
Devices (Note 1)
Number of DQS Delay Buffer
–3
–4
Unit
1
28
30
ps
2
56
60
ps
3
84
90
ps
4
112
120
ps
Note to Table 1–61:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay
buffers in a 3 speed grade is ± 84 ps or ± 42 ps.
Table 1–62 lists the memory output clock jitter specifications for Arria II GX devices.
Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices (Note 1), (2), (3)
Parameter
Clock
Network
Symbol
–4
Min
Max
–5
Min
Max
–6
Unit
Min
Max
Clock period jitter
Global
t_JIT(per)
-100
100
-125
125
-125
125 ps
Cycle-to-cycle period
jitter
Global
t_JIT(cc)
-200
200
-250
250
-250
250 ps
Duty cycle jitter
Global
t_JIT(duty)
-100
100
-125
125
-125
125 ps
Notes to Table 1–62:
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global
clock network.
(3) The memory output clock jitter stated in Table 1–62 is applicable when an input jitter of 30 ps is applied.
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation