EP2AGX190FF35C4N Datasheet, PDF (21/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum

Chapter 1: Device Datasheet for Arria II Devices
Electrical Characteristics
1–13
Table 1–17 lists the pin capacitance for Arria II GZ devices.
Table 1–17. Pin Capacitance for Arria II GZ Devices
Symbol
Description
Typical
Unit
C_IOTB
Input capacitance on the top and bottom I/O pins
4
pF
C_IOLR
Input capacitance on the left and right I/O pins
4
pF
C_CLKTB
Input capacitance on the top and bottom non-dedicated clock input pins
4
pF
C_CLKLR
Input capacitance on the left and right non-dedicated clock input pins
4
pF
C_OUTFB
Input capacitance on the dual-purpose clock output and feedback pins
5
pF
C_CLK1, C_CLK3, C_CLK8,
and C_CLK10
Input capacitance for dedicated clock input pins
2
pF
Internal Weak Pull-Up and Weak Pull-Down Resistors
Table 1–18 lists the weak pull-up and pull-down resistor values for Arria II GX
devices.
Table 1–18. Internal Weak Pull-up and Weak Pull-Down Resistors for Arria II GX Devices (Note 1)
Symbol Description
Conditions
Min
Typ
Max
Unit
V_CCIO = 3.3 V ±5% (2)
7
25
41
k
Value of I/O pin pull-up resistor V_CCIO = 3.0 V ±5% (2)
7
R_PU
before and during configuration,
as well as user mode if the
V_CCIO = 2.5 V ±5% (2)
programmable pull-up resistor ^{VCCIO = 1.8 V ±5% (2)}
8
10
option is enabled.
V_CCIO = 1.5 V ±5% (2)
13
28
47
k
35
61
k
57
108
k
82
163
k
V_CCIO = 1.2 V ±5% (2)
19
143
351
k
V_CCIO = 3.3 V ±5%
6
19
29
k
V_CCIO = 3.0 V ±5%
R_PD
Value of TCK pin pull-down
resistor
V_CCIO = 2.5 V ±5%
V_CCIO = 1.8 V ±5%
6
22
32
k
6
25
42
k
7
35
70
k
V_CCIO = 1.5 V ±5%
8
50
112
k
Notes to Table 1–18:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for
JTAG TCK.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO.
July 2012 Altera Corporation
Arria II Device Handbook Volume 3: Device Datasheet and Addendum