EP2AGX190FF35C4N Datasheet, PDF (68/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum

1–60
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Configuration
Table 1–50 lists the configuration mode specifications for Arria II GX and GZ devices.
Table 1–50. Configuration Mode Specifications for Arria II Devices
Programming Mode
DCLK Frequency
Unit
Min
Typ
Max
Passive serial
Fast passive parallel
Fast active serial (fast clock)
Fast active serial (slow clock)
Remote update only in fast AS mode
—
—
125
MHz
—
—
125
MHz
17
26
40
MHz
8.5
13
20
MHz
—
—
10
MHz
JTAG Specifications
Table 1–51 lists the JTAG timing parameters and values for Arria II GX and GZ
devices.
Table 1–51. JTAG Timing Parameters and Values for Arria II Devices
Symbol
t_JCP
t_JCH
t_JCL
t_{JPSU (TDI)}
t_{JPSU (TMS)}
t_JPH
t_JPCO
t_JPZX
t_JPXZ
Description
TCK clock period
TCK clock high time
TCK clock low time
TDI JTAG port setup time
TMS JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Min
Max
Unit
30
—
ns
14
—
ns
14
—
ns
1
—
ns
3
—
ns
5
—
ns
—
11
ns
—
14
ns
—
14
ns
Chip-Wide Reset (Dev_CLRn) Specifications
Table 1–52 lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX
and GZ devices.
Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices
Description
Min
Typ
Max Unit
Dev_CLRn
500
—
—
s
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation