EP2AGX190FF35C4N Datasheet, PDF (29/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum

Switching Characteristics
This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade
devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers
reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions.
Transceiver Performance Specifications
Table 1–34 lists the Arria II GX transceiver specifications.
Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 1 of 7)
Symbol/
Description
Condition
Min
I3
C4
C5 and I5
C6
Unit
Typ
Max Min Typ
Max
Min
Typ
Max Min Typ Max
Reference Clock
Supported I/O
Standards
Input frequency
from REFCLK
—
input pins
Input frequency
from PLD input
—
Absolute V_MAX
for a REFCLK pin
—
Absolute V_MIN for
a REFCLK pin
—
Rise/fall time (2)
—
Duty cycle
—
Peak-to-peak
differential input
—
voltage
Spread-spectrum
modulating clock PCIe
frequency
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
50
—
622.08 50
—
622.08
50
—
622.08 50
— 622.08 MHz
50
—
200
50
—
200
50
—
200
50 —
200
MHz
—
—
2.2
—
—
2.2
—
—
2.2
——
2.2
V
–0.3
—
—
–0.3 —
—
–0.3
—
—
–0.3 —
—
V
—
—
0.2
—
—
0.2
—
—
0.2
——
0.2
UI
45
—
55
45
—
55
45
—
55
45 —
55
%
200
—
2000 200 —
2000
200
—
2000 200 — 2000
mV
30
—
33
30
—
33
30
—
33
30 —
33
kHz