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EP2AGX190FF35C4N Datasheet, PDF (62/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum | |||
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1â54
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1â44. PLL Specifications for Arria II GX Devices (Part 2 of 3)
Symbol
Description
Min Typ
Max
Unit
Output frequency for internal global or regional clock
(â4 Speed Grade)
â
â
500
MHz
fOUT
Output frequency for internal global or regional clock
(â5 Speed Grade)
â
â
500
MHz
Output frequency for internal global or regional clock
(â6 Speed Grade)
â
â
400
MHz
Output frequency for external clock output (â4 Speed Grade)
â
â
670 (5)
MHz
fOUT_EXT
Output frequency for external clock output (â5 Speed Grade)
â
â
622 (5)
MHz
Output frequency for external clock output (â6 Speed Grade)
â
â
500 (5)
MHz
tOUTDUTY Duty cycle for external clock output (when set to 50%)
45
50
tOUTPJ_DC
Dedicated clock output period jitter (fOUT ï³ 100 MHz)
Dedicated clock output period jitter (fOUT ï¼ 100 MHz)
â
â
â
â
tOUTCCJ_DC
Dedicated clock output cycle-to-cycle jitter (fOUT ï³ 100 MHz)
Dedicated clock output cycle-to-cycle jitter (fOUT ï¼ 100 MHz)
â
â
â
â
fOUTPJ_IO
Regular I/O clock output period jitter (fOUT ï³ 100 MHz)
Regular I/O clock output period jitter (fOUT ï¼ 100 MHz)
â
â
â
â
fOUTCCJ_IO
Regular I/O clock output cycle-to-cycle jitter (fOUT ï³ 100 MHz)
Regular I/O clock output cycle-to-cycle jitter (fOUT ï¼ 100 MHz)
â
â
â
â
tCONFIGPLL Time required to reconfigure PLL scan chains
â
3.5
55
%
300
ps (pâp)
30
mUI (pâp)
300
ps (pâp)
30
mUI (pâp)
650
ps (pâp)
65
mUI (pâp)
650
ps (pâp)
65
mUI (pâp)
â
SCANCLK
cycles
tCONFIGPHASE Time required to reconfigure phase shift
â
1
â
SCANCLK
cycles
fSCANCLK
tLOCK
tDLOCK
SCANCLK frequency
Time required to lock from end of device configuration
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
â
â
100
MHz
â
â
1
ms
â
â
1
ms
PLL closed-loop low bandwidth
â
0.3
â
MHz
fCL B W
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
â
1.5
â
MHz
â
4
â
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
Minimum pulse width on areset signal
â
â
±50
ps
10
â
â
ns
Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation
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