EP2AGX190FF35C4N Datasheet, PDF (36/90 Pages) Altera Corporation – Volume 3: Device Datasheet and Addendum

1–28
Chapter 1: Device Datasheet for Arria II Devices
Switching Characteristics
Table 1–35 lists the transceiver specifications for Arria II GZ devices.
Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 1 of 5)
Symbol/
Description
Conditions
–C3 and –I3 (1)
Min Typ
Max
–C4 and –I4
Unit
Min Typ
Max
Reference Clock
Supported I/O Standards
Input frequency from
REFCLK input pins
Phase frequency detector
(CMU PLL and receiver
CDR)
Absolute V_MAX for a REFCLK
pin
Operational V_MAX for a
REFCLK pin
Absolute V_MIN for a REFCLK
pin
Rise/fall time (2)
Duty cycle
Peak-to-peak differential
input voltage
Spread-spectrum
modulating clock frequency
Spread-spectrum
downspread
On-chip termination
resistors
V_ICM (AC coupled)
V_ICM (DC coupled)
Transmitter REFCLK Phase
Noise
Transmitter REFCLK Phase
Jitter (rms) for 100 MHz
REFCLK (3)
R_REF
1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL
—
50
—
697
50
—
637.5 MHz
—
50
—
325
50
—
325 MHz
—
—
—
1.6
—
—
—
1.5
—
-0.4
—
—
—
—
—
0.2
—
45
—
55
—
200
—
1600
PCIe
PCIe
—
—
HCSL I/O standard
for PCIe reference
clock
10 Hz
100 Hz
1 KHz
10 KHz
100 KHz
 1 MHz
30
—
33
0 to
—
—
-0.5%
—
100
—
1100 ± 10%
250
—
550
—
—
-50
—
—
-80
—
—
-110
—
—
-120
—
—
-120
—
—
-130
10 KHz to 20 MHz —
—
3
—
—
2000 ±
1%
—
—
—
1.6
V
—
—
1.5
V
-0.4 —
—
V
—
—
0.2
UI
45
—
55
%
200
—
1600 mV
30
—
33
kHz
0 to
—
—
—
-0.5%
—
100
—

1100 ± 10%
mV
250
—
550
mV
—
—
-50 dBc/Hz
—
—
-80 dBc/Hz
—
—
-110 dBc/Hz
—
—
-120 dBc/Hz
—
—
-120 dBc/Hz
—
—
-130 dBc/Hz
—
—
3
ps
—
2000 ±
1%
—

Arria II Device Handbook Volume 3: Device Datasheet and Addendum
July 2012 Altera Corporation