EP2S180 Datasheet, PDF (7/58 Pages) Altera Corporation – DSP Development Board

1. Introduction
General
Description
Stratix II
EP2S180 DSP
Devlopment
Board
The Stratix II EP2S180 DSP development board provides a hardware
platform that designers can use to develop DSP systems based on
Stratix II devices. Combined with DSP intellectual property (IP) from
Altera and partners in the Altera Megafunction Partners Program
(AMPP^SM), users can quickly develop powerful DSP systems. Altera’s
unique OpenCore^® Plus technology allows users to evaluate MegaCore^®
functions in hardware prior to licensing them.
DSP Builder, version 5.0.1 includes a library for the Stratix II EP2S180 DSP
development board. This library allows algorithm development,
simulation, and verification on the board, all from within the MathWorks
MATLAB/Simulink system-level design tool. Additionally, the Stratix II
DSP development board includes a Texas Instrument EVM (cross-
platform) daughter card connector, which enables development and
verification of FPGA co-processors for off loading and accelerating
compute-bound algorithms from programmable DSP processors.
The Stratix^® II EP2S180 DSP development board is included with the DSP
Development Kit, Stratix II Professional Edition (ordering code DSP-
DEVKIT-2S180). This board is a development platform for
high-performance digital signal processing (DSP) designs, and features
the Stratix II EP2S180 device in a 1020-pin package.
Components
■ Analog I/O
● Two 12-bit 125-MHz A/D converters
● Two 14-bit 165-MHz D/A converters
● One 8-bit, 180 megapixels-per-second triple D/A converter for
VGA output
● One 96-KHz Stereo Audio coder/decoder (CODEC)
■ Memory subsystem
● 1 MByte of 10-ns asynchronous SRAM configured as a 32-bit bus
● 16 MBytes of flash memory configured as an 8-bit bus
● 32 MBytes of SDRAM memory configured as a 64-bit bus
● CompactFlash connector supporting ATA and IDE access modes
■ Configuration options
● On-board configuration using 16 MBytes of flash memory and
an Altera^® EPM7256 MAX^® device
Altera Corporation
August 2005
Core Version a.b.c variable
1–1
Preliminary