EP2S180 Datasheet, PDF (30/58 Pages) Altera Corporation – DSP Development Board

Board Components
Table 2–18. D/A B (U15, J17) Stratix II Pin-Outs
Signal Name
dacB_D1 (MSB) (1)
dacB_D2
dacB_D3
dacB_D4
dacB_D5
dacB_D6
dacB_D7
dacB_D8
dacB_D9
dacB_D10
dacB_D11
dacB_D12
dacB_D13
dacB_D14 (LSB)
Stratix II Pin
W4
W5
Y6
Y7
Y8
Y9
Y10
Y11
AB5
AB6
AA10
AA11
AA6
AA7
Note to Table 2–18:
(1) The Texas Instruments (TI) naming conventions differ from those of Altera
Corporation. The TI data sheet for the DAC 904 D/A converter lists bit 1 as the
most significant bit (MSB) and bit 14 as the least significant bit (LSB).
SRAM Memory (U43 & U44)
U43 and U44 are two 256 Kbyte x 16-bit asynchronous SRAM devices.
They are connected to the Stratix II device so they can be used by a
Nios^® II embedded processor as general-purpose memory. The two 16-bit
devices can be used in parallel to implement a 32-bit wide memory
subsystem. Refer to Table 2–19 for Stratix II device pin-outs for SRAM
devices U43 and U44.
Table 2–19. SRAM Memory (U43 & U44) (Part 1
of 3)
Pin Name
SE_A0
SE_A1
SE_A2
SE_A3
SE_A4
Pin Number
AD8
AM27
AM28
AJ27
AK27
2–22
Core Version a.b.c variable
Stratix II EP2S180 DSP Development Board Reference Manual
Altera Corporation