EP2S180 Datasheet, PDF (25/58 Pages) Altera Corporation – DSP Development Board

Board Components & Interfaces
to select the clock for ADC B. Table 2–10 explains how to select these three
clock signals. The selected clock will pass through a differential LVPECL
buffer before arriving at the clock input to both A/D converters
Table 2–10. A/D Clock Source Settings
J3, J4 Setting
Pins 1 and 2
Pins 3 and 4
Pins 5 and 6
Clock Source
Signal Name
Stratix II PLL
circuitry
adc_PLLCLK1,
adc_PLLCLK2
OSC or External adc_CLK_IN1,
input clock positive adc_CLK_IN2
OSC or External adc_CLK_IN1_n,
input clock negative adc_CLK_IN2_n
Table 2–11 lists reference information for the A/D converters.
Table 2–11. A/D Converter Reference
Item
Board reference
Part number
Device description
Voltage
Manufacturer
Manufacturer web site
Description
U1, U2
AD9433BSQ
12-bit, 125-MSPS A/D converter
3.3-V digital V_DD, 5.0-V analog V_DD
Analog Devices
www.analog.com
Altera Corporation
Core Version a.b.c variable
2–17
Stratix II EP2S180 DSP Development Board Reference Manual