EP3C5_1 Datasheet, PDF (30/34 Pages) Altera Corporation – Cyclone III Device Data Sheet

1–30
Chapter 1: Cyclone III Device Data Sheet
Glossary
Table 1–39. Glossary (Part 4 of 5)
Letter
Term
t_C
TCCS (Channel-
to-channel-skew)
tcin
tC O
tcout
tDUTY
T
tFA LL
tH
Timing Unit
Interval (TUI)
tINJITTER
tOUTJITTER_DEDC LK
tOUTJITTER_IO
tpllcin
tpllcout
Definitions
High-speed receiver/transmitter input and output clock period.
HIGH-SPEED I/O Block: The timing difference between the fastest and slowest output edges,
including t_CO variation and clock skew. The clock is included in the TCCS measurement.
Delay from clock pad to I/O input register.
Delay from clock pad to I/O output.
Delay from clock pad to I/O output register.
HIGH-SPEED I/O Block: Duty cycle on high-speed transmitter output clock.
Signal High-to-low transition time (80–20%).
Input register hold time.
HIGH-SPEED I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t_C/w).
Period jitter on PLL clock input.
Period jitter on dedicated clock output driven by a PLL.
Period jitter on general purpose I/O driven by a PLL.
Delay from PLL inclk pad to I/O input register.
Delay from PLL inclk pad to I/O output register.
Transmitter Output Waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards
Single-Ended Waveform
Transmitter
Output Waveform
VOD
Vos
Positive Channel (p) = V_OH
Negative Channel (n) = V_OL
Ground
t_RISE
t_{S U}
U
—
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V_OD
0V
V_OD
p-n
Signal Low-to-high transition time (20–80%).
Input register setup time.
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Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation