EP3C5_1 Datasheet, PDF (18/34 Pages) Altera Corporation – Cyclone III Device Data Sheet

1–18
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.
Table 1–25. Cyclone III Devices JTAG Timing Parameters (Note 1)
Symbol
Parameter
Min Max Unit
t_{JC P}
TCK clock period
40 — ns
tJC H
TCK clock high time
20 — ns
tJC L
TCK clock low time
20 — ns
tJPSU_TDI JTAG port setup time for TDI (2)
1
— ns
tJPSU_TMS JTAG port setup time for TMS (2)
3
— ns
tJP H
JTAG port hold time
10 — ns
tJP CO
JTAG port clock to output (2)
— 15 ns
tJP Z X
JTAG port high impedance to valid output (2)
— 15 ns
tJP XZ
JTAG port valid output to high impedance (2)
— 15 ns
tJS SU
Capture register setup time (2)
5
— ns
tJS H
Capture register hold time
10 — ns
tJS CO
Update register clock to output
— 25 ns
tJS Z X
Update register high impedance to valid output
— 25 ns
tJS XZ
Update register valid output to high impedance
— 25 ns
Notes to Table 1–25:
(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.
Periphery Performance
High-Speed I/O Specifications
Table 1–26 through Table 1–31 list the high-speed I/O timing for Cyclone III devices.
For definitions of high-speed timing specifications, refer to “Glossary” on page 1–27.
Table 1–26. Cyclone III Devices RSDS Transmitter Timing Specifications (Note 1), (2) (Part 1 of 2)
Symbol
f_{H SC L K}
(input clock
frequency)
Modes
×10
×8
×7
×4
×2
×1
C6
C7, I7
C8, A7
Unit
Min Typ Max Min Typ Max Min Typ Max
10 — 180 10 — 155.5 10 — 155.5 MHz
10 — 180 10 — 155.5 10 — 155.5 MHz
10 — 180 10 — 155.5 10 — 155.5 MHz
10 — 180 10 — 155.5 10 — 155.5 MHz
10 — 180 10 — 155.5 10 — 155.5 MHz
10 — 360 10 — 311 10 — 311 MHz
Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation