EP3C5_1 Datasheet, PDF (21/34 Pages) Altera Corporation – Cyclone III Device Data Sheet

Chapter 1: Cyclone III Device Data Sheet
1–21
Switching Characteristics
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (Note 1)
Symbol
Modes
C6
Min Max
C7, I7
Min Max
C8, A7
Min Max
×10
10 420 10 370 10 320
×8
10 420 10 370 10 320
f_HSCLK (input
×7
clock frequency)
×4
10 420 10 370 10 320
10 420 10 370 10 320
×2
10 420 10 370 10 320
×1
10 420 10 402.5 10 402.5
×10
100 840 100 740 100 640
×8
80 840 80 740 80 640
HSIODR
×7
70 840 70 740 70 640
×4
40 840 40 740 40 640
×2
20 840 20 740 20 640
×1
10 420 10 402.5 10 402.5
tDUTY
TCCS
—
45
55
45
55
45
55
—
— 200 — 200 — 200
Output jitter
(peak to peak)
—
— 500 — 500 — 550
t_LOCK (2)
—
—
1
—
1
—
1
Notes to Table 1–29:
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
ps
ps
ms
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (Note 1) (Part 1
of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min Max Min Max Min Max
×10
×8
f_HSCLK (input clock
×7
frequency)
×4
×2
×1
×10
×8
×7
HSIODR
×4
×2
×1
tDUTY
—
10 320 10 320 10 275 MHz
10 320 10 320 10 275 MHz
10 320 10 320 10 275 MHz
10 320 10 320 10 275 MHz
10 320 10 320 10 275 MHz
10 402.5 10 402.5 10 402.5 MHz
100 640 100 640 100 550 Mbps
80 640 80 640 80 550 Mbps
70 640 70 640 70 550 Mbps
40 640 40 640 40 550 Mbps
20 640 20 640 20 550 Mbps
10 402.5 10 402.5 10 402.5 Mbps
45
55
45
55
45
55
%
© January 2010 Altera Corporation
Cyclone III Device Handbook, Volume 2