EP3C5_1 Datasheet, PDF (16/34 Pages) Altera Corporation – Cyclone III Device Data Sheet

1–16
Chapter 1: Cyclone III Device Data Sheet
Switching Characteristics
Table 1–20. Cyclone III Devices PLL Specifications (Note 1) (Part 2 of 2)
Symbol
Parameter
Min Typ Max
Unit
PLL output frequency (–6 speed grade)
—
— 472.5
MHz
fOUT (to global clock)
PLL output frequency (–7 speed grade)
PLL output frequency (–8 speed grade)
—
—
450
MHz
—
— 402.5
MHz
tOUTDUTY
tLOCK
t_DLOCK
Duty cycle for external clock output (when set to 50%) 45
50
55
%
Time required to lock from end of device configuration —
—
1
ms
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
—
—
1
ms
areset is deasserted)
t (5) _{OUTJITTER_PERIOD_DEDCLK}
t (5) OUTJITTER_CCJ_DEDCLK
t (5) OUTJITTER_PERIOD_IO
t (5) OUTJITTER_CCJ_IO
t_{PL L_ PS ERR}
t_ARESET
t_{CONF IGPLL}
Dedicated clock output period jitter
F_OUT ≥ 100 MHz
F_OUT < 100 MHz
Dedicated clock output cycle-to-cycle jitter
F_OUT ≥ 100 MHz
F_OUT < 100 MHz
Regular I/O period jitter
F_OUT ≥ 100 MHz
F_OUT < 100 MHz
Regular I/O cycle-to-cycle jitter
F_OUT ≥ 100 MHz
F_OUT < 100 MHz
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
—
—
300
ps
—
—
30
mUI
—
—
300
ps
—
—
30
mUI
—
—
650
ps
—
—
75
mUI
—
—
650
ps
—
—
75
mUI
—
—
±50
ps
10
—
—
ns
—
3.5 (6)
—
SCANCLK
cycles
f_{SC AN C L K}
scanclk frequency
—
—
100
MHz
Notes to Table 1–20:
(1) VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead.
(2) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(3) The V_CO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the V_CO post-scale
counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 200 ps.
(5) Peak-to-peak jitter with a probability level of 10^–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic
jitter of the PLL, when an input jitter of 30 ps is applied.
(6) With 100 MHz scanclk frequency.
Cyclone III Device Handbook, Volume 2
© January 2010 Altera Corporation