1GB-AUTO-AS4C128M8D3 Datasheet, PDF (82/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
Figure 75. Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Td0
Td1
CK#
CK
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
Last async.
ODT
RTT
Sync. or
async. ODT
RTT
First sync.
ODT
RTT
tANPD
RTT
tAOFPD(min)
tAOFPD(max)
RTT
tAOFPD(min)
PD exit transition period
tXPDLL
ODTLoff + tAOF(min)
tAOFPD(max)
ODTLoff + tAOF(max)
RTT
TIME BREAK
ODTLoff
tAOF(min)
TRANSITIONING DATA
tAOF(max)
Don't Care
Figure 76. Transition period for short CKE cycles, entry and exit period overlapping
(AL = 0, WL = 5, tANPD = WL - 1 = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
CK#
CK
COMMAND
REF
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CKE
CKE
tANPD
tANPD
tRFC (min)
PD entry transition period
PD exit transition period
tANPD
short CKE low transition period
short CKE high transition period
tXPDLL
tXPDLL
TIME BREAK
Don't Care
Confidential
-82-
Rev.1.0 May 2015