1GB-AUTO-AS4C128M8D3 Datasheet, PDF (36/84 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

1Gb Auto-AS4C128M8D3
l Jitter Notes
NOTE 1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one
Mode Register Set command is registered at Tm, another Mode Register Set command may be
registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
NOTE 2. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#,
ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec
values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup
and hold are relative to the clock signal crossing that latches the command/address. That is, these
parameters should be met whether clock jitter is present or not.
NOTE 3. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective
clock signal (CK, CK#) crossing. The spec values are not affected by the amount of clock jitter
applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these
parameters should be met whether clock jitter is present or not.
NOTE 4. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its
respective data strobe signal (DQS, DQS#) crossing.
NOTE 5. For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] /
tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
NOTE 6. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM
input clock.)
NOTE 7. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
Table 21. Input clock jitter spec parameter
Parameter
Clock period jitter
Clock period jitter during DLL locking period
Cycle to cycle clock period jitter
Cycle to cycle clock period jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
Cumulative error across n cycles, n=13...50, inclusive
Symbol
-12BAN
Min.
Max.
Unit
t_JIT (per)
-70
70
ps
t_JIT (per,lck)
-60
60
ps
t_JIT (cc)
140
ps
t_JIT (cc,lck)
120
ps
t_ERR (2per)
-103
103
ps
t_ERR (3per)
-122
122
ps
t_ERR (4per)
-136
136
ps
t_ERR (5per)
-147
147
ps
t_ERR (6per)
-155
155
ps
t_ERR (7per)
-163
163
ps
t_ERR (8per)
-169
169
ps
t_ERR (9per)
-175
175
ps
t_ERR (10per)
-180
180
ps
t_ERR (11per)
-184
184
ps
t_ERR (12per)
-188
188
ps
t_ERR (nper)
t_ERR (nper)_min = (1+0.68ln(n)) * t_JIT (per)_min
t_ERR (nper)_max = (1+0.68ln(n)) * t_JIT (per)_max
ps
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Rev.1.0 May 2015